//=============================================================================
// File Name : 6410addr.h
// Function  : S3C6410 Define Address Register
//=============================================================================

#ifndef __6410ADDR_H__
#define __6410ADDR_H__

#ifdef __cplusplus
extern "C" {
#endif

#define __BYTEREG(pa)   *(volatile unsigned char*)((virtaddr_t)((pa) - 0x70000000 + 0x80000000))
#define __SHORTREG(pa)  *(volatile unsigned short*)((virtaddr_t)((pa) - 0x70000000 + 0x80000000))
#define __REG(pa)  *(volatile unsigned *)((virtaddr_t)((pa) - 0x70000000 + 0x80000000))
#define __VIR(pa)  ((virtaddr_t)((pa) - 0x70000000 + 0x80000000))

// INTERRUPT

#define VIC0_BASE				(0x71200000)
#define VIC1_BASE				(0x71300000)
// VIC0
#define	rVIC0IRQSTATUS			__REG(VIC0_BASE + 0x00)
#define	rVIC0FIQSTATUS			__REG(VIC0_BASE + 0x04)
#define	rVIC0RAWINTR			__REG(VIC0_BASE + 0x08)
#define	rVIC0INTSELECT			__REG(VIC0_BASE + 0x0c)
#define	rVIC0INTENABLE			__REG(VIC0_BASE + 0x10)
#define	rVIC0INTENCLEAR			__REG(VIC0_BASE + 0x14)
#define	rVIC0SOFTINT			__REG(VIC0_BASE + 0x18)
#define	rVIC0SOFTINTCLEAR		__REG(VIC0_BASE + 0x1c)
#define	rVIC0PROTECTION			__REG(VIC0_BASE + 0x20)
#define	rVIC0SWPRIORITYMASK		__REG(VIC0_BASE + 0x24)
#define	rVIC0PRIORITYDAISY		__REG(VIC0_BASE + 0x28)

#define rVIC0VECTADDR			__REG(VIC0_BASE + 0x100)
#define VIC0VECTADDR            __VIR(VIC0_BASE + 0x100)
#define rVIC0VECPRIORITY		__REG(VIC0_BASE + 0x200)
#define VIC0VECPRIORITY         __VIR(VIC0_BASE + 0x200)

#define rVIC0ADDR				__REG(VIC0_BASE + 0xf00)
#define rVIC0PERID0				__REG(VIC0_BASE + 0xfe0)
#define rVIC0PERID1				__REG(VIC0_BASE + 0xfe4)
#define rVIC0PERID2				__REG(VIC0_BASE + 0xfe8)
#define rVIC0PERID3				__REG(VIC0_BASE + 0xfec)
#define rVIC0PCELLID0			__REG(VIC0_BASE + 0xff0)
#define rVIC0PCELLID1			__REG(VIC0_BASE + 0xff4)
#define rVIC0PCELLID2			__REG(VIC0_BASE + 0xff8)
#define rVIC0PCELLID3			__REG(VIC0_BASE + 0xffc)

// VIC1
#define	rVIC1IRQSTATUS			__REG(VIC1_BASE + 0x00)
#define	rVIC1FIQSTATUS			__REG(VIC1_BASE + 0x04)
#define	rVIC1RAWINTR			__REG(VIC1_BASE + 0x08)
#define	rVIC1INTSELECT			__REG(VIC1_BASE + 0x0c)
#define	rVIC1INTENABLE			__REG(VIC1_BASE + 0x10)
#define	rVIC1INTENCLEAR			__REG(VIC1_BASE + 0x14)
#define	rVIC1SOFTINT			__REG(VIC1_BASE + 0x18)
#define	rVIC1SOFTINTCLEAR		__REG(VIC1_BASE + 0x1c)
#define	rVIC1PROTECTION			__REG(VIC1_BASE + 0x20)
#define	rVIC1SWPRIORITYMASK		__REG(VIC1_BASE + 0x24)
#define	rVIC1PRIORITYDAISY		__REG(VIC1_BASE + 0x28)

#define rVIC1VECTADDR			__REG(VIC1_BASE + 0x100)
#define VIC1VECTADDR            __VIR(VIC1_BASE + 0x100)
#define rVIC1VECPRIORITY		__REG(VIC1_BASE + 0x200)
#define VIC1VECPRIORITY         __VIR(VIC1_BASE + 0x200)

#define rVIC1ADDR				__REG(VIC1_BASE + 0xf00)
#define rVIC1PERID0				__REG(VIC1_BASE + 0xfe0)
#define rVIC1PERID1				__REG(VIC1_BASE + 0xfe4)
#define rVIC1PERID2				__REG(VIC1_BASE + 0xfe8)
#define rVIC1PERID3				__REG(VIC1_BASE + 0xfec)
#define rVIC1PCELLID0			__REG(VIC1_BASE + 0xff0)
#define rVIC1PCELLID1			__REG(VIC1_BASE + 0xff4)
#define rVIC1PCELLID2			__REG(VIC1_BASE + 0xff8)
#define rVIC1PCELLID3			__REG(VIC1_BASE + 0xffc)


// PWM TIMER
#define rTCFG0  __REG(0x7f006000)	//Timer 0 configuration
#define rTCFG1  __REG(0x7f006004)	//Timer 1 configuration
#define rTCON   __REG(0x7f006008)	//Timer control
#define rTCNTB0 __REG(0x7f00600c)	//Timer count buffer 0
#define rTCMPB0 __REG(0x7f006010)	//Timer compare buffer 0
#define rTCNTO0 __REG(0x7f006014)	//Timer count observation 0
#define rTCNTB1 __REG(0x7f006018)	//Timer count buffer 1
#define rTCMPB1 __REG(0x7f00601c)	//Timer compare buffer 1
#define rTCNTO1 __REG(0x7f006020)	//Timer count observation 1
#define rTCNTB2 __REG(0x7f006024)	//Timer count buffer 2
#define rTCMPB2 __REG(0x7f006028)	//Timer compare buffer 2
#define rTCNTO2 __REG(0x7f00602c)	//Timer count observation 2
#define rTCNTB3 __REG(0x7f006030)	//Timer count buffer 3
#define rTCMPB3 __REG(0x7f006034)	//Timer compare buffer 3
#define rTCNTO3 __REG(0x7f006038)	//Timer count observation 3
#define rTCNTB4 __REG(0x7f00603c)	//Timer count buffer 4
#define rTCNTO4 __REG(0x7f006040)	//Timer count observation 4
#define rTINTCSTAT __REG(0x7f006044)	//Timer interrupt control and status reg


// WATCH DOG TIMER
#define rWTCON   __SHORTREG(0x7e004000)	//Watch-dog timer mode
#define rWTDAT   __SHORTREG(0x7e004004)	//Watch-dog timer data
#define rWTCNT   __SHORTREG(0x7e004008)	//Eatch-dog timer count


// RTC
#define rRTCCON    __BYTEREG(0x7e005040)	//RTC control
#define rTICNT         __REG(0x7e005044)	    //Tick time count
#define rRTCALM    __BYTEREG(0x7e005050)	//RTC alarm control
#define rALMSEC    __BYTEREG(0x7e005054)	//Alarm second
#define rALMMIN    __BYTEREG(0x7e005058)	//Alarm minute
#define rALMHOUR   __BYTEREG(0x7e00505c)	//Alarm Hour
#define rALMDATE   __BYTEREG(0x7e005060)	//Alarm date  // edited by junon
#define rALMMON    __BYTEREG(0x7e005064)	//Alarm month
#define rALMYEAR   __BYTEREG(0x7e005068)	//Alarm year
#define rBCDSEC    __BYTEREG(0x7e005070)	//BCD second
#define rBCDMIN    __BYTEREG(0x7e005074)	//BCD minute
#define rBCDHOUR   __BYTEREG(0x7e005078)	//BCD hour
#define rBCDDATE   __BYTEREG(0x7e00507c)	//BCD date  //edited by junon
#define rBCDDAY    __BYTEREG(0x7e005080)	//BCD day   //edited by junon
#define rBCDMON    __BYTEREG(0x7e005084)	//BCD month
#define rBCDYEAR   __BYTEREG(0x7e005088)	//BCD year

// PENDING BIT
#define BIT_EINT0		(0x1)
#define BIT_EINT1		(0x1<<1)
#define BIT_EINT2		(0x1<<2)
#define BIT_EINT3		(0x1<<3)
#define BIT_EINT4_7		(0x1<<4)
#define BIT_EINT8_23	(0x1<<5)
#define BIT_CAM			(0x1<<6)		// Added for 6410.
#define BIT_BAT_FLT		(0x1<<7)
#define BIT_TICK			(0x1<<8)
#define BIT_WDT_AC97	(0x1<<9)
#define BIT_TIMER0		(0x1<<10)
#define BIT_TIMER1		(0x1<<11)
#define BIT_TIMER2		(0x1<<12)
#define BIT_TIMER3		(0x1<<13)
#define BIT_TIMER4		(0x1<<14)
#define BIT_UART2		(0x1<<15)
#define BIT_LCD			(0x1<<16)
#define BIT_DMA0		(0x1<<17)
#define BIT_DMA1		(0x1<<18)
#define BIT_DMA2		(0x1<<19)
#define BIT_DMA3		(0x1<<20)
#define BIT_SDI			(0x1<<21)
#define BIT_SPI0			(0x1<<22)
#define BIT_UART1		(0x1<<23)
#define BIT_NFCON		(0x1<<24)		// Added for 6410.
#define BIT_USBD		(0x1<<25)
#define BIT_USBH		(0x1<<26)
#define BIT_IIC			(0x1<<27)
#define BIT_UART0		(0x1<<28)
#define BIT_SPI1			(0x1<<29)
#define BIT_RTC			(0x1<<30)
#define BIT_ADC			(0x1<<31)
#define BIT_ALLMSK		(0xffffffff)

#define BIT_SUB_ALLMSK	(0x7fff)
#define BIT_SUB_AC97 	(0x1<<14)
#define BIT_SUB_WDT 	(0x1<<13)
#define BIT_SUB_ADC		(0x1<<10)
#define BIT_SUB_TC		(0x1<<9)
#define BIT_SUB_ERR2	(0x1<<8)
#define BIT_SUB_TXD2	(0x1<<7)
#define BIT_SUB_RXD2	(0x1<<6)
#define BIT_SUB_ERR1	(0x1<<5)
#define BIT_SUB_TXD1	(0x1<<4)
#define BIT_SUB_RXD1	(0x1<<3)
#define BIT_SUB_ERR0	(0x1<<2)
#define BIT_SUB_TXD0	(0x1<<1)
#define BIT_SUB_RXD0	(0x1<<0)

#define	ClearPending(bit) {\
		}
//Wait until rINTPND is changed for the case that the ISR is very short.


#ifdef __cplusplus
}
#endif
#endif  //__6410ADDR_H__
